Programmable logic controller questions
tzn789
MODULE TITLE: PROGRAMMABLE LOGIC CONTROLLERS
TOPIC TITLE: THE STRUCTURE OF THE PLC
LESSON 3: SYSTEM FEATURES II
PLC - 5 - 3
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________________________________________________________________________________________
INTRODUCTION ________________________________________________________________________________________
This lesson, like the previous one, examines the internal structure and
operation of a PLC. Such structure is established by running a computer
program using a standard microprocessor-based system. It must be stressed
therefore that the operation is largely dependent upon the programmer who
writes the firmware for the system. In our examination we are not discussing
the structural features of any one manufacturer's system. Rather, we are
making a logical interpretation of the features we would require of such a
system.
Variations of these features are highlighted at relevant points and are used to
form the basis of an analysis of a program run. The lesson should therefore be
considered as a description of the operation of a PLC model which we
ourselves may have constructed.
Initially we shall be refreshing our understanding of CPU memories with the
aid of the CPU block diagram.
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________________________________________________________________________________________
YOUR AIMS ________________________________________________________________________________________
Upon completion of this lesson you should be able to:
• understand the use of types of memory required by PLCs
• understand methods of storing a program listing
• understand the operation of a data table
• explain the operation of certain microprocessor logic instructions
• follow the execution of a scan sequence at machine code level.
________________________________________________________________________________________
STUDY ADVICE ________________________________________________________________________________________
Where references are made to instruction sets and instruction operation the
Zilog Z80 processor has been used as the example. The use of the Z80 falls in
line with its use in other modules of this course.
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________________________________________________________________________________________
SYSTEM OPERATION ________________________________________________________________________________________
From the block diagram of the PLC system (FIGURE 1) it can be seen that the
onboard memory (memory within the PLC) falls into three types:
read only memory (ROM)
battery-backed RAM
ordinary RAM (non battery-backed).
However, these are types of memory and don't give any indication as to the
way they are used. We know already that the ROM contains the monitor
(executive) program which runs when the power is first applied. We also
know that the battery-backed RAM is used to hold the user program so that if
the power supply fails and is then restored the user does not need to key-in the
program again.
Additionally the user program is always available so that it may be called up
for checking or alteration purposes.
The third type of memory, the non battery-backed RAM, holds data which may
be continually changing (we can refer to this part as a data table) and it may
also hold a version of the user program which the CPU can run at high speed
i.e. a machine code version. The memory may, therefore, be shown with the
names of the functions performed rather than with the names of the memory
type. FIGURE 2 shows this.
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FIG. 1
FIG. 2
Monitor/Executive program
(Firmware)
User version of ladder diagram listing/program
Retentive data
Machine code version of ladder diagram
program
Data table
Read Only Memory
Battery-backed Read/Write
Memory (RAM)
Non battery- backed Read/Write
Memory (RAM)
MEMORY
External inputs
External loads
System clock
Power supply
ROM Communications
interface CPU
microprocessor
Display
Input interface
Ouput interface
I/O interface adaptor
Memory
Keyboard
Mode selector
Halt Monitor
Run
Battery backed RAM
Non battery backed RAM
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When the PLC is switched to the PROGRAM MODE the executive program
provides access to the USER VERSION of the program listing. With this
mode selected the user can update, change or examine parts of the listing by
using the keyboard to state the requirements.
When the selector is switched to the RUN MODE a sequence of operations is
initiated. The user version of the ladder diagram (the program listing), which
may or may not have been altered since the previous run, is checked for syntax
errors. This means that the listing is analysed to ensure that the correct
programming format has been followed. It does not check for the correct
operation of the program. Only the user/programmer knows how the program
is expected to work.
The occurrence of syntax errors is usually indicated on the display. Should any
errors exist the program will not normally run. Errors must be corrected by
returning to the program mode and altering the program listing. Typical error
messages are:
No end instruction
Circuit error
Coil duplication error
All memory used.
If no errors exist then the user version of the ladder diagram (the program
listing) will be converted by a part of the executive program into a machine
code version, which will be placed in a reserved area of the RAM.
The data table will be cleared of data left over from any previous run. Note at
this point that devices specified as retentive are not normally cleared at this
time. This can cause a program run to behave in an unexpected manner and so
care is needed when using such retentive devices. Sometimes a special
instruction is provided to ensure that retentive devices are cleared (reset) before
the program runs for the first time.
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The inputs are read and an image of them is placed in the input data table.
(Possible variations of this will be examined in examples.)
The machine code version of the program will then be run.
The inputs/relays etc. will be checked against the program requirements and an
image of the outputs established in the output data table.
At the point in the listing where an END instruction appeared, the equivalent
machine code version causes the output data image to be sent to the output
interface circuitry thereby updating the physical outputs.
The program then reverts back to the part in the sequence where the inputs are
again read and the input data table updated. Note that the whole sequence is
carried out only once, and thereafter the shorter version is repeated. There is
no point in checking for correct syntax every time the sequence is repeated. If
it was acceptable the first time and the program mode has not subsequently
been selected then it must still be acceptable.
Each time the operation passes through the sequence it is said to have been
through one SCAN. The time taken is called the scan time and this is normally
measured in microseconds (or milliseconds). The physical outputs are
therefore updated very quickly following changes in the input conditions. This
high speed can give the impression that the PLC is doing many things at once
which is, in fact, not the case.
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________________________________________________________________________________________
MACHINE CODE OPERATION ________________________________________________________________________________________
The last lesson on system operation outlined a sequence of events which could
occur when our PLC is switched to the run mode. There are parts of this
sequence which need further expansion to clarify the operation of our PLC
model. The system facilities used when a program listing is entered into a
PLC will determine the method used to store and interpret the program.
At this point we will consider three possibilities.
1. If the programmer unit is the type which displays a single line of a
program listing then this line may be converted into a machine code
sequence and be stored away in memory immediately the 'write to
memory' key is pressed. This means that the only version of the user
program to be stored would be the machine code version and, therefore,
less memory would be used. However, this method may present problems
when the syntax check is carried out. Additionally, when the user wishes
to look back through the program listing, the machine code version must
be read and decoded back into a form suitable for the display.
2. A second possibility is for each ladder diagram function to be stored as a
code (sometimes called tokens) followed by data representing details of
the operand. This is a fairly straightforward method when it comes to the
syntax check because formations or groupings of tokens are looked for.
Each token, followed by data, can be easily decoded to supply the display
information. When the PLC is switched to RUN and after the syntax
check has been made, the tokens and data would be converted into the
high speed machine code version of the program before being run for the
first time.
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3. The third possibility, and one which is likely to be used when using a
personal computer as the programmer unit, is that the listing would be
entered as text and stored in an area of memory called a text buffer. From
here it would be copied into other memory circuits, such as the video
RAM so that it may be displayed on a cathode-ray tube monitor. Entering
the text program requires an editor/assembler combination to provide the
syntax check before the machine code version is assembled and
subsequently run.
For the case when the listing is stored as text, relatively large amounts of
battery-backed RAM need to be provided to be able to store the listing through
a power failure. Every character of the text must have a code to represent it
i.e. a code for each letter, number, space, delimiter, carriage return, etc. and not
just a code for every function as in the case of tokens. If an industry standard
code, such as the ASCII code, is used then standard utility driver programs can
be utilised to send the codes to the video screen, or to a line printer or to send
them downline to other PLCs requiring the same program.
Whichever method is employed the system must be able to display the listing
in a suitable form whenever the user switches from the RUN mode to the
PROGRAM mode. The facility of editing must also be provided in order to
make additions/alterations to the program listing.
To obtain an impression of how much memory would be needed if the ASCII
code were used, we can examine the storage of one rung of a ladder diagram.
Consider the rung of FIGURE 3.
FIG. 3
X001 X002 Y000X003
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The listing for this rung could be:
STEP OP-CODE OPERAND
000 LD X001
001 AND X002
002 AND X003
003 OUT Y000
When this is keyed in it would become the ASCII listing shown overleaf.
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Address Hexadecimal code Character held in memory represented
Some suitable start address 4C L address +1 44 D address +2 09 delimiter (separator) address +3 58 X address +4 30 0 address +5 30 0 address +6 31 1 address +7 1E end of element code address +8 41 A address +9 4E N address +10 44 D address +11 09 delimiter address +12 58 X address +13 30 0 address +14 30 0 address +15 32 2 address +16 1E end of element code address +17 41 A address +18 4E N address +19 44 D address +20 09 delimiter address +21 58 X address +22 30 0 address +23 30 0 address +24 33 3 address +25 1E end of element code address +26 4F O address +27 55 U address +28 54 T address +29 09 delimiter address +30 59 Y address +31 30 0 address +32 30 0 address +33 30 0 address +34 1E end of element code
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It is easy to see that this method uses up lots of memory.
Now that we have an idea of how the program listing may be stored, perhaps
we should ask the question "what will the machine code version look like?"
Before considering this question the operating principles of our data table need
to be examined.
The data table is merely our name for a specified area within the RAM. This
area will consist of a number of unique locations, each one having its own
address number. To allow a relatively short explanation we will assume that
the microprocessor we are using has an eight bit data bus i.e. a byte of data is
handled per instruction. If we make a further assumption that our PLC model
has eight digital inputs and eight digital outputs then the explanation should be
that much simpler.
FIGURE 4 illustrates, in a simplified way, the arrangement.
FIG. 4
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Microcomputer
Input interface
Output interface
CInput common
8 Inputs
Input terminals
C
Output terminals
Output common
8 Outputs
Programmable Logic Controller
Each input supplies one bit of information, therefore eight bits of information
are supplied in total from all of the inputs. We shall also make the assumption
that if an input switch is closed then a logic 1 is read at the input interface. If,
on the other hand, an input switch is open then we would expect a logic 0 to be
read. So if, for example, three of the input switches are closed then three logic
1's and five logic 0's will be read at the input interface.
This is illustrated by the diagram of FIGURE 5.
FIG. 5
Assume that input switches 6, 2 and 0 were all closed, producing a bit pattern
of 01000101 (or Hexadecimal value 45). The microprocessor would be
supplied with this value if the inputs were read at this time.
X000 X007
External wiring
The eight bit positions placed
together form 1 byte of data.
Input data register 00 101010
Closed position of an input switch indicated by a 1 in the
input data register.
Input Interface Circuit
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Similarly if input switches 7,6,4 and 1 were all closed the bit pattern 11010010
(D2 Hex) would be read.
In just the same way the eight outputs should have logic levels associated with
them. A logic 1 supplied by the microprocessor can be used to turn on an
output and a logic 0 can be used to turn off an output, or vice versa. The
position within the byte dictates which output is switched on or off. The
diagram of FIGURE 6 illustrates this.
FIG. 6
With this configuration the outputs 7, 4, 2 and 1 can be switched on by
outputting the bit pattern 10010110 (96 Hex). To change the outputs from this
to switch on 7, 6, 5, 1 and 0 the bit pattern would be changed to become
11100011 (E3 Hex). Once changed the bit pattern must be latched i.e. locked
at these values until the next change is required.
Output common
Output data register
Y000Y007
Output terminals
On On On Off Off Off On On
Common
11111 00 0
Output Interface Circuit
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In our model the microprocessor handles eight bits of data at a time. This
means, therefore, that all inputs can be read at the same time and all eight
outputs can be controlled/altered at once.
If our system had 16 inputs and 8 outputs then the inputs would be read-in in
two sets of eight bits and the outputs switched by one set of eight bits.
________________________________________________________________________________________
INPUT DATA TABLE ________________________________________________________________________________________
The input data must be read and a copy of it stored within the input data table.
Two methods of manipulating and storing the input port data will be
considered.
METHOD 1
The first method is the simplest. The microprocessor merely reads the eight
data bits available at the input port and stores them in one memory location
which is one byte wide. This forms a copy, or image, of the state of the inputs
at that point in time, in memory.
FIGURE 7 shows this.
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FIG. 7
The exact address in memory which is used by the microprocessor is not
important to us but it is vitally important to the PLC. The same address would
need to be used for the input image each time the inputs were read for the
purpose of updating the table. This is because the processor would need to
refer to the contents of this address when running the machine code program.
METHOD 2
The second method is slightly more complicated but it does make the design
and running of the machine code program simpler at a later stage.
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Load the input data into the accumulator
X000
Input data register
X007
00 101110 00 101110
00 101110
Store the input data in the input image address in
memory
Address for
X007 – X000
Memory addresses for the data image
Accumulator
Input Interface Circuit
With this method the eight data bits are read in and then manipulated so that
they are stored in eight different (but sequential) memory addresses within the
data table.
This could be considered a waste of memory space, as it takes up eight times
as much memory as method 1, but it does have its advantages.
Each of the eight data bits must end up in the least significant position in the
eight selected addresses. The other seven bit positions in each address are
given a 0 value. The diagram of FIGURE 8 illustrates this.
FIG. 8
X000
Input data register
X007
00 101110
00 101110
All other memory cells are given a zero value
Memory address
Memory addresses for the data image
0
1
1
1
1
0
0
X007
X006
X005
X004
0 0 0
0 0
0
Input terminals
Working register
0
Input Interface Circuit
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How can this be achieved?
Going back to your previous microelectronics experience you will appreciate
that the method used will depend upon the particular processor being
employed. However, the process can be broken down into steps as it would
need to be to form the manipulation program.
Step 1
Flush the input data table i.e. load each location with 0 in each bit position (00
Hex).
Step 2
Read the input port placing the eight data bits into a working register (say the
B register).
Step 3
Shift the eight bits in the B register, one bit to the right such that the first bit is
placed into the carry flag. In most microprocessor instruction sets the SRL
instruction is used to achieve this.
FIG. 9
Register Carry flag
Zero donated by the operation
0 01 010100 1
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Step 4
Check the carry flag to see if it is set, i.e. contains a 1. If it does then place
(load) the bit pattern 00000001 (01 Hex) into the first address in the input data
table. If it does not then place (load) the bit pattern 00000000 (00 Hex) into
this address.
Step 5
Repeat the shift right operation of step 3.
FIG. 10
Step 6
Examine the carry flag. If it contains a 1 then place (load) the bit pattern
00000001 (01 Hex) in the next location in the input data table. If it contains a
0 then place the bit pattern 00000000 (00 Hex) into this location.
Steps 7 to 18 are repeats of steps 5 and 6
This manipulation fills up the input data table with an image of the states of the
inputs.
Register Carry flag
Zero donated by the operation
0 11 100000 0
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Where an address contains the bit pattern 00000001 (01 Hex) it means that the
associated input has a closed switch and where an address contains the bit
pattern 00000000 (00 Hex) it means that the associated input has its switch
open.
Here again the same addresses in the input data table memory must be used
each time the inputs are read and the data table updated.
The program used to load the input data table would probably use an index
register to keep track of the current input table address being handled i.e. the X
index register in connection with the (X) inputs.
Before considering what to do with the data held in the input data table it
would be wise to revise some basic knowledge on the subject of logic, which
should help you to follow the explanations given later.
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Inputs Output
B A Q
0 0 0
0 1 0
1 0 0
1 1 1
LOGIC
To obtain a better understanding of how the microprocessor handles logic
commands we shall re-examine some basic logic operations that we have met
in previous lessons.
Three logic functions will be covered:
(a) the AND function
(b) the OR function
and (c) the NOT function.
THE AND FUNCTION We have mentioned the AND function in previous lessons. Let us consider a
2 input AND gate and use this to show how the AND instruction is carried out
within a microprocessor.
Truth Table
A Inputs &
B
Q Output
FIG. 11
FIGURE 11 shows the B.S. symbol and the truth table for a 2 input AND gate.
From the truth table it can be seen that the output from the gate is always a
logic 0 unless both inputs are a logic 1 at the same time.
In a microprocessor the AND instruction logically combines two sets of input
binary patterns. One set would be held in a temporary storage device called
the working register (or more commonly the accumulator). The other set
would be obtained from another location within the system. The exact location
would need to be specified by the instruction.
We will assume that we are using a microprocessor which handles one byte
(eight bits) of data at a time. Each binary pattern must, therefore, have eight
characters. (Remember that a binary character is either a 1 or a 0.)
For the purpose of our explanation we shall place a bit pattern of 10110111 in
the accumulator and a second bit pattern of 01100110 in another register (say
the B register). If, now, the microprocessor receives the instruction 'AND B',
the operation performed will effectively use eight separate 2 input gates.
Each gate will handle one bit from each of the accumulator and B registers.
The result is eight outputs – some may be logic 1 and some logic 0, depending
upon the inputs to each gate.
After the AND instruction this eight bit result is placed back into the
accumulator and overwrites the previous contents.
Careful examination of the two bit patterns shows that a 1 results only when
two 1's are present at the inputs of the same gate. This is shown in
FIGURE 12.
FIG. 12
B Register contents
Accumulator contents
Accumulator contents
=
=
=
0 1 1 0 0 1 1 0
1 0 1 1 0 1 1 1
0 0 1 0 0 1 1 0
Before 'AND B'
After 'AND B'
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FIGURE 13 shows the functional arrangement, for the bit patterns specified,
during the handling of the 'AND B' instruction.
FIG. 13
THE OR FUNCTION
FIGURE 14 shows the B.S. symbol for a two input OR gate together with its
truth table.
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Accumulator with original
contents
00 011110
01 111101
Result going into the
accumulator
Accumulator Bit pattern after
the 'AND B' instruction
Result of the 'AND B' instruction
B register bit pattern
&
&
&
&
&
&
&
&
00 011100
0
0
1
1
0
0
0
1
FIG. 14
Examination of the truth table shows that the gate output will be a logic 1 if
any or all inputs are at logic 1.
In a microprocessor the OR instruction logically 'combines' two sets of input
binary patterns. If we again use the eight bit binary patterns from the previous
explanation i.e.
the B register contains 01100110
and the Accumulator contains 10110111
then, when the microprocessor receives the 'OR B' instruction, the following
will be performed.
Eight two-input OR gates will each receive one bit from each of the
accumulator and the B register – the result will be eight outputs which will
be placed back into the accumulator overwriting the previous contents.
FIGURE 15 shows the functional arrangement when handling these bit patterns.
Inputs Output
AB
01
10
00
11
Truth Table
A
B
Q OutputInputs 1
1
1
1
0
Q
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FIG. 15
THE NOT FUNCTION
The NOT gate (or inverter) was covered as an inverting buffer within the
lessons covering the interfacing topic.
To refresh our memory, the gate has one input and one output. The output is
always the opposite logic level from that applied at the input.
The B.S. symbol and truth table are shown in FIGURE 16.
Accumulator with original
contents
00 011110
01 111101
Result going into the
accumulator
Accumulator Bit pattern after
the 'OR B' instruction
Result of the 'OR B' instruction
B register bit pattern
1
1
1
1
1
1
1
1
01 111111
1
1
1
1
1
1
0
1
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FIG. 16
The instruction used by a microprocessor to produce an inversion is called the
COMPLEMENT (or one's complement). If the complement instruction is
executed on the eight bit accumulator previously considered, then after the
instruction every 0 will have been changed to a 1 and every 1 will have been
changed to a 0.
e.g. If the accumulator contains 10110111 before the complement (CPL)
instruction then it will contain 01001000 afterwards.
FIGURE 17 on page 26 shows the functional arrangement while handling the
CPL instruction.
Input Output
Truth Table
Output Q
Input A
0
1
Q
1
0
A
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FIG. 17
Accumulator with original
contents
01 111101
Result going into the
accumulator
Accumulator Bit pattern after
the CPL instruction
Result of the CPL instruction
0
1
0
0
0
0
1
0
10 000010
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Complete the following examples by 'ANDing' the two sets of eight bits.
(a) 01100011 = A
10100010 = B
............... = A AND B
(b) 11110000 = A
10101111 = B
............... = A AND B
(c) 00000001 = A
00000000 = B
............... = A AND B
(d) 00000001 = A
00000001 = B
............... = A AND B
Complete the following examples by 'ORing' the two sets of eight bits.
(e) 01100011 = A
10100010 = B
............... = A OR B = A + B
(f) 11110000 = A
10101111 = B
............... = A + B
(g) 00000001 = A
00000000 = B
............... = A + B
(h) 00000001 = A
00000001 = B
............... = A + B
________________________________________________________________________________________
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Answers are given below.
(a) 00100010 = A AND B
(b) 10100000 = A AND B
(c) 00000000 = A AND B
(d) 00000001 = A AND B
(e) 11100011 = A OR B
(f) 11111111 = A OR B
(g) 00000001 = A OR B
(h) 00000001 = A OR B
________________________________________________________________________________________
OUTPUT DATA TABLE ________________________________________________________________________________________
The output data table could be considered in a similar way to the input data
table. Obviously a different set of RAM addresses would need to be allocated
so that input data and output data are not confused. As in method 1 for the
input table, one address could be used to hold the state of eight outputs or, as in
method 2, eight separate sequential addresses could be used.
If method 1 is used then the condition of an output could be regarded as being
switched on by placing a logic 1 in a suitable bit position. Setting a bit to the
'on state' may be achieved in some processors by the use of a SET BIT
instruction or by the use of a logical OR instruction.
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If method 2 is used then setting a bit merely requires the loading/storing of a
bit pattern of 00000001 (01 Hex) into the correct address within the output
data table. Switching an output image off (when a rung is not complete) must
also be a part of the program.
For method 1 a reset bit instruction (RES) would be used.
For method 2 the particular address would be loaded with 00000000 (00 Hex).
During the execution of the machine code version of the user program the
output data table would be updated by having those outputs specified in the
listing set or reset by one of the methods indicated above. At the time when
the physical outputs are to be updated the output data image is sent out to the
output latches or interface adaptor.
If method 1 is used then this simply means copying the output data table image
bit pattern and sending it to the output interface circuit.
If method 2 is used then the eight separate memory locations representing our
output table memory must have the relevant data bits collected together to
form one byte to be sent to the output interface.
The diagram of FIGURE 18 shows an output data table using method 2. The
relevant data bits are the least significant bits in each memory location. Each
of these bits is collected in sequence to form the data byte shown in the
accumulator, before being sent to the output data register which supplies the
output interface.
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FIG. 18
How is this manipulation achieved?
As with the loading of the input data table for method 2 the process can be
broken down into a sequence of steps.
Output data register
Output data image
Y007
Y006
Y005
Y004
00 110111
00 110111
Output data table
addresses
Accumulator
0
All other memory cells contain zeros
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
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Step 1
The contents of the address for output Y007 are loaded into the accumulator.
The contents shown in FIGURE 18 are 00000001 (01 Hex).
Step 2
A shift left one bit position instruction is now used to alter the positioning of
the data bits. FIGURE 19 illustrates steps 1 and 2.
FIG. 19
Step 3
The accumulator contents are logically 'ORed' with the contents of the address
for output Y006. Bit 1 of the accumulator had a 1 after the first shift
instruction. FIGURE 18 shows that address Y006 has a 1 in its bit 0 position.
After step 3, therefore, the accumulator has a bit pattern of 00000011 (03 Hex).
Load accumulator with
Y007 contents
Shift left one bit
00 100000
00 010000
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Step 4
The accumulator contents are again shifted one bit to the left. FIGURE 20
shows steps 3 and 4.
FIG. 20
Step 5
The accumulator contents are logically 'ORed' with the contents of the address
for Y005. FIGURE 18 shows this address to have bit 0 set at 1. After step 5,
therefore, the accumulator has a bit pattern of 00000111 (07 Hex).
Step 6
The accumulator contents are again shifted one bit to the left. FIGURE 21
shows steps 5 and 6.
Logical OR the accumulator with
Y006 contents
Shift left one bit
00 110000
00 011000
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FIG. 21
Step 7
The accumulator contents are logically 'ORed' with the contents of the address
for Y004. FIGURE 18 shows this address to have all zeros. After step 7,
therefore, the accumulator has a bit pattern of 00001110 (0E Hex).
Step 8
The accumulator contents are again shifted one bit to the left. FIGURE 22
shows steps 7 and 8.
FIG. 22
Logical OR the accumulator with
Y004 contents
Shift left one bit
10 011000
11 001000
Logical OR the accumulator with
Y005 contents
Shift left one bit
00 111000
10 011000
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The steps continue in the same sequence until all of the eight bits have been
collected. By comparing the following diagrams with that of FIGURE 18 you
should be able to check out the process.
FIG. 23
FIG. 24
FIG. 25
Logical OR the accumulator with
Y001 contents
Shift left one bit
01 100110
00 010111
Logical OR the accumulator with
Y002 contents
Shift left one bit
11 000100
01 000110
Logical OR the accumulator with
Y003 contents
Shift left one bit
11 001000
11 000100
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Finally the accumulator is logically 'ORed' with the contents of the address for
Y000.
After this operation all eight bits have been collected and are now ready to be
sent to the output data register.
FIG. 26
So far we have considered the data table as an area in RAM which is used to
store an image of the inputs and outputs. However, some other addresses in
this RAM must similarly be allocated for use as internal memory relays as well
as for other uses not yet considered. The diagram of FIGURE 27 can be used
Output common
Output data register
Y000Y007
Output terminals
On On On Off Off Off On On
Common
11111 00 0
11111 00 0 Logical OR the
accumulator with Y000 contents
Output Interface Circuit
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to represent the way in which the memory addresses could be allocated for
each purpose. (The diagram assumes only eight inputs, eight outputs and eight
memory relays and also that method 2 is being used.)
FIG. 27
Address locations holding
data
Continuation of memory
Input data
image
Output data
image
Memory relay data
image R003
R002
R001
R000
R007
R006
R005
R004
Y003
Y002
Y001
Y000
Y007
Y006
Y005
Y004
X003
X002
X001
X000
X007
X006
X005
X004
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Now that the loading and retrieval of data held in the data table has been
examined we are ready to consider the way in which the table forms part of the
operating procedure. To do this we will again carry out a step by step
sequence which, this time, takes us through the handling of a ladder diagram
listing. Our examination of the procedure will assume that method 2 has been
adopted for the format of the data stored in the data table. As previously
mentioned, the use of method 2 makes the machine code version of the listing
easier to understand.
The ladder diagram of FIGURE 28 will be used for the procedural analysis.
FIG. 28
When the listing for the above diagram has been entered and the mode switch
changed from PROGRAM to RUN the following sequence is carried out.
X004
R001
X007 R000 Y000
X002
Y000
R000
Y002
X001 X003 R000
X005
R001
End
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Step 1
The listing is checked for correct syntax and, if acceptable, is converted into a
machine code program. The program is stored in memory for use later.
Step 2
The data table is flushed i.e. all non-retentive memory addresses are cleared by
being loaded with 00000000 (00 Hex).
Step 3
The input conditions are read and the input data table is loaded.
Step 4
The machine code version of the ladder diagram listing is now run. We shall
examine this in rungs.
Rung 1 (a) The contents of address X001 are loaded into the accumulator.
(b) The accumulator contents are ANDed with the contents of
address X003.
(c) The accumulator contents are ANDed with the contents of
address X005.
(d) The accumulator is now tested to see if it contains a 01 Hex
value. If it does then 01 Hex is loaded into the address for
R000, if not, then 00 Hex is loaded.
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Rung 2 (a) The contents of address X007 are loaded into the accumulator.
(b) The accumulator contents are ANDed with the contents of
address R000.
(c) The accumulator is now tested to see if it contains a 01 Hex
value. If it does, then 01 Hex is loaded into the address for
Y000, if not, then 00 Hex is loaded.
Rung 3 (a) The contents of address R001 are loaded into the accumulator.
(b) The accumulator contents are ORed with the contents of
address X004.
(c) The accumulator contents are ANDed with the contents of
address Y000.
(d) The accumulator is now tested to see if it contains a 01 Hex
value. If it does, then 01 Hex is loaded into the address for
Y002, if not then 00 Hex is loaded.
Rung 4 (a) The contents of address X002 are loaded into the accumulator.
(b) The contents of the accumulator are stored in a second register.
The contents of address R000 are loaded into the accumulator.
The accumulator contents are complemented before being
ANDed with the contents of the second register.
(c) The accumulator is now tested to see if it contains a 01 Hex
value. If it does, then 01 Hex is loaded into the address for
R001, if not then 00 Hex is loaded.
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Step 5
The END instruction is converted into meaning: copy the output data table and
send it to the output data register so that the physical outputs may be updated.
Step 6
Go back to the beginning of the execution of the machine code program and
repeat the sequence i.e. go back to Step 3.
This same sequence:
i.e. Read the data in / update the input data table.
Execute the machine code program / alter the table as necessary.
Update the state of the physical outputs.
is repeated over and over again until the PLC mode is changed, either to HALT
or back to PROGRAM, or the machine is switched off.
The previous sequence of steps can be represented by a simple flowchart as
shown in FIGURE 29 opposite.
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FIG. 29
Now attempt the Self-Assessment Questions.
Read in the inputs and load the input data table
Switch to RUN mode
Check listing for syntax errors
Clear the data table
Execute the machine code program until the END
instruction
Send out a copy of the output data table to the
output interface
Report any errors, wait for corrections
Scan loop
If none found, change the listing into a machine code
version and store in memory
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________________________________________________________________________________________
SELF-ASSESSMENT QUESTIONS ________________________________________________________________________________________
Your self-assessment for this lesson is one exercise.
FIGURE 30 shows a ladder diagram involving the use of inputs, memory
relays and outputs.
FIG.30
The exercise requires you to trace the sequence of events affecting the data
table through four complete scan loops. At the time of the mode change to
RUN the inputs are as shown in the prevailing input conditions diagram
(FIGURE 31(a)). At the end of the first scan and before the second scan
begins the inputs change to the new conditions shown in FIGURE 31(b). Data
table method 2 is to be used.
X006
X001
R000
R000
R003 R001
X000 R001 R000
X002
Y000
R003
End
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FIG. 31
Complete the diagrams of the blank data tables but be careful to complete them
sequentially.
FIGURE 32 shows a blank data table. Complete this table by filling in the
Hexadecimal values expected just before the first run of the machine code
program.
Prevailing input conditions
New conditions
X007
X007 X000
X000
(a)
(b)
11 111100
11 111110
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FIG. 32
Now complete the next diagram (FIGURE 33) by filling in the data expected
after the first scan. Remember the prevailing conditions exist before this scan.
Continuation of memory
Input data
image
Output data
image
Memory relay data
image R003
R002
R001
R000
R007
R006
R005
R004
Y003
Y002
Y001
Y000
Y007
Y006
Y005
Y004
X003
X002
X001
X000
X007
X006
X005
X004
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FIG. 33
Now complete the next diagram (FIGURE 34) by filling in the expected data
after the second scan. The new input conditions exist before this scan.
Continuation of memory
Input data
image
Output data
image
Memory relay data
image R003
R002
R001
R000
R007
R006
R005
R004
Y003
Y002
Y001
Y000
Y007
Y006
Y005
Y004
X003
X002
X001
X000
X007
X006
X005
X004
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FIG. 34
Now complete the next diagram (FIGURE 35) by filling in the data expected
after the third scan. The new input conditions still exist.
Continuation of memory
Input data
image
Output data
image
Memory relay data
image R003
R002
R001
R000
R007
R006
R005
R004
Y003
Y002
Y001
Y000
Y007
Y006
Y005
Y004
X003
X002
X001
X000
X007
X006
X005
X004
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FIG. 35
The last diagram (FIGURE 36) is to hold the data expected after the fourth
scan. The same input conditions exist.
Continuation of memory
Input data
image
Output data
image
Memory relay data
image R003
R002
R001
R000
R007
R006
R005
R004
Y003
Y002
Y001
Y000
Y007
Y006
Y005
Y004
X003
X002
X001
X000
X007
X006
X005
X004
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FIG. 36
Continuation of memory
Input data
image
Output data
image
Memory relay data
image R003
R002
R001
R000
R007
R006
R005
R004
Y003
Y002
Y001
Y000
Y007
Y006
Y005
Y004
X003
X002
X001
X000
X007
X006
X005
X004
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Once the tables have been completed answer the following questions:
(a) How many scans does it take before R001 is switched on?
(b) How long does Y000 stay on?
(c) At the end of the fourth scan which memory relays are switched on?
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________________________________________________________________________________________
ANSWERS TO SELF-ASSESSMENT QUESTIONS ________________________________________________________________________________________
The diagram of FIGURE 37 shows the Hexadecimal contents of the data table
through the four scans.
FIG. 37
Memory address
Input data
image
Output data
image
Memory relay data
image R003
R002
R001
R000
R007
R006
R005
R004
Y003
Y002
Y001
Y000
Y007
Y006
Y005
Y004
X003
X002
X001
X000
X007
X006
X005
X004
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Cleared data table
After first scan
After second scan
After third scan
After fourth scan
01
01
01
01
00
00
01
01
01
01
01
01
00
01
01
01
00
00
00
01
00
00
00
00
01
00
00
00
00
00
00
00
00
00
00
01
00
00
00
00
01
01
01
01
00
01
01
01
00
00
00
01
00
00
00
00
01
00
01
00
00
00
00
00
01
00
01
01
00
00
00
00
01
01
01
01
00
01
01
01
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(a) R001 is switched on during the third scan.
(b) The exact time duration of Y000 being switched on cannot be stated due
to insufficient information being available. However, we can see that it
remains on for the time taken for three scans (probably about 30
milliseconds).
(c) The memory relays expected to be switched on after the fourth scan are
R000, R001 and R003. These relays are memory cells and, as such,
cannot be seen.
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________________________________________________________________________________________
SUMMARY ________________________________________________________________________________________
This lesson was intended to provide an insight into the possible internal
behaviour of a PLC. As was stressed in the introduction, the internal operation
of any PLC is largely determined by the person who designs the firmware.
This stores and converts the ladder diagram program listing before it is
executed as a high speed machine code microprocessor program.
To overcome the dependence upon someone else's firmware, this lesson
approached the subject by viewing some of the possibilities available if we
were concerned with making a new design. You should not make the mistake
of thinking that the methods put forward here are the only methods from which
we can choose. Our method of using the scan to interrogate each rung element
in turn may, for example, be replaced with a scan which interrogates elements
within vertical columns and not across horizontal rungs. However, the
methods we have examined are realistic and could be included in any system.
The self-assessment question was the real test of your understanding of the
methods discussed. If you did not obtain the same answers as those provided
then you should attempt the exercise again. If you still experience problems
then, as always, contact your tutor.
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setdistillerparams << /HWResolution [2400 2400] /PageSize [612.000 792.000] >> setpagedevice