MIPS RISC architectures Questionssterlingmano
1) Why is the presence of a hardwired zero register so important in RISC architectures?
2) The MIPS ISA does not include a negate instruction. Provide another MIPS assembly instruction that negates the contents of register 3 and writes the result into register 4.
3) How many registers can a register specifier of 7 bits address?
4) Name one key benefit and one key drawback of large register specifiers.
5) Compute the address from which the load byte instruction below reads, the address to which the branch transfers control if taken, and the address that is the target of the jump instruction.
0x80000000: lui $t2, 1
0x80000004: lb $t3, 1($t2)
0x80000008: beq $t3, $zero, 1
0x8000000C: j 1
6) Is it more important to include a floating-point multiplication instruction or an integer multiplication instruction in the ISA of a new processor family and why?
7) The offset in a beq instruction can only reach about ±215 instructions. What needs to be done if the target instruction is further away, i.e., the offset is too small? Write down the necessary sequence of MIPS assembly instructions; including the correct offset (do not use a label).
8) Why is the value from the immediate field in branch instructions shifted by two bits before it is used but the value from the immediate field in load and store instructions is not shifted before it is used?
9) The MIPS ISA has no “ble a, b, label” (branch less than or equal to) instruction. Provide a sequence of two MIPS assembly instructions that will accomplish the “ble” operation.
10) Explain how the effective address of a load or store instruction is computed in MIPS.
- 8 years ago
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